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<title>NOP—No Operation </title></head>
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<h1>NOP—No Operation</h1>
<table>
<tr>
<th>Opcode</th>
<th>Instruction</th>
<th>Op/En</th>
<th>64-Bit Mode</th>
<th>Compat/Leg Mode</th>
<th>Description</th></tr>
<tr>
<td>90</td>
<td>NOP</td>
<td>NP</td>
<td>Valid</td>
<td>Valid</td>
<td>One byte no-operation instruction.</td></tr>
<tr>
<td>0F 1F /0</td>
<td>NOP r/m16</td>
<td>M</td>
<td>Valid</td>
<td>Valid</td>
<td>Multi-byte no-operation instruction.</td></tr>
<tr>
<td>0F 1F /0</td>
<td>NOP r/m32</td>
<td>M</td>
<td>Valid</td>
<td>Valid</td>
<td>Multi-byte no-operation instruction.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>NP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>M</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>This instruction performs no operation. It is a one-byte or multi-byte NOP that takes up space in the instruction stream but does not impact machine context, except for the EIP register.</p>
<p>The multi-byte form of NOP is available on processors with model encoding:</p>
<p>The multi-byte NOP instruction does not alter the content of a register and will not issue a memory operation. The instruction’s operation is the same in non-64-bit modes and 64-bit mode.</p>
<h2>Operation</h2>
<p>The one-byte NOP instruction is an alias mnemonic for the XCHG (E)AX, (E)AX instruction.</p>
<p>The multi-byte NOP instruction performs no operation on supported processors and generates undefined opcode exception on processors that do not support the multi-byte NOP instruction.</p>
<p>The memory operand form of the instruction allows software to create a byte sequence of “no operation” as one instruction. For situations where multiple-byte NOPs are needed, the recommended operations (32-bit mode and 64-bit mode) are:</p>
<h3>Table 4-12.  Recommended Multi-Byte Sequence of NOP Instruction</h3>
<table>
<tr>
<th>Length</th>
<th>Assembly</th>
<th>Byte Sequence</th></tr>
<tr>
<td>
<p>2 bytes</p>
<p>3 bytes</p>
<p>4 bytes</p>
<p>5 bytes</p>
<p>6 bytes</p>
<p>7 bytes</p>
<p>8 bytes</p>
<p>9 bytes</p></td>
<td>
<p>66 NOP</p>
<p>NOP DWORD ptr [EAX]</p>
<p>NOP DWORD ptr [EAX + 00H]</p>
<p>NOP DWORD ptr [EAX + EAX*1 + 00H]</p>
<p>66 NOP DWORD ptr [EAX + EAX*1 + 00H]</p>
<p>NOP DWORD ptr [EAX + 00000000H]</p>
<p>NOP DWORD ptr [EAX + EAX*1 + 00000000H]</p>
<p>66 NOP DWORD ptr [EAX + EAX*1 + 00000000H]</p></td>
<td>
<p>66 90H</p>
<p>0F 1F 00H</p>
<p>0F 1F 40 00H</p>
<p>0F 1F 44 00 00H</p>
<p>66 0F 1F 44 00 00H</p>
<p>0F 1F 80 00 00 00 00H</p>
<p>0F 1F 84 00 00 00 00 00H</p>
<p>66 0F 1F 84 00 00 00 00 00H</p></td></tr></table>
<h2>Flags Affected</h2>
<p>None</p>
<h2>Exceptions (All Operating Modes)</h2>
<p>#UD</p>
<p>If the LOCK prefix is used.</p></body></html>